The use of signal processors, such as, for example, digital signal processors (DSPs), for supporting multiple data rates in certain applications is well known. Such applications may include, for example, read channels for hard disk drives supporting a wide range of data rates because the disk spins at a constant angular velocity, read channels for optical storage supporting multiple data rates (e.g., 1×, 2×, 4×, 8× read speeds), and Ethernet or wireless local area network (LAN) transceivers supporting multiple data rates (e.g., 10/100/1000/10000 megabits per second (Mb/s) for Gigabit Ethernet).
In many data processing circuits, the DSP is a primary source of power consumption in the circuits. For certain applications, particularly portable applications, reducing power consumption is critical. Conventional methodologies for reducing power consumption in a data processing circuit generally involve operating the DSP at a lower supply voltage for lower data rates. However, operating the DSP at a lower supply voltage has several disadvantages. For example, operating the DSP at a lower supply voltage for lower data rates requires the use of expensive voltage regulators. Furthermore, the amount by which the supply voltage can be reduced is limited by worst case transistor threshold voltage levels in the circuit (e.g., about 0.85 volt, depending on the integrated circuit process technology) and the amount of overdrive required in the circuit (the term “overdrive” generally refers to the level of gate voltage above the threshold voltage required for a given transistor device).
Accordingly, there exists a need for techniques for reducing power consumption in a DSP circuit which do not suffer from one or more of the above-described problems associated with conventional DSP circuitry.